Multilayer ceramic capacitors for decoupling applications require the use of high k (dielectric constant) dielectric to provide the necessary capacitance. However, for high performance applications, in an interposer configuration, this high dielectric capacitance between signal vias can cause excessive parasitic capacitance/noise, thus detracting from the performance of the decoupling capacitor or "decap". Therefore, while a high k ceramic is required for the capacitor, it is a detriment in the immediate vicinity of signal vias.
Multilayer ceramic (MLC) capacitors are frequently used to suppress the voltage noise generated by circuits in semiconductor chips. This noise arises as a result of voltage fluctuations generated across power bus lines during the simultaneous switching of circuits. This noise can degrade chip performance. Further, as circuit densities increase and rise times decrease, and supply voltage levels decrease, the simultaneous switching problem gets exacerbated. This can seriously impede chip performance at high frequencies of operation.
Decoupling capacitors are used as a means to reduce the extent of this problem. Typical low inductance MLC discrete decaps are made using relatively high permittivity ceramic materials which enable the delivery of high capacitance. These may be made in the parallel plate configuration with a plurality of termination points on either side which act as the two electrodes, which may be then connected to power and ground respectively. Such low inductance decaps can provide 30 to 200 nF per discrete MLC capacitor of less than 2 mm.times.2 mm.times.2 mm size. However the inductance associated with these discrete decaps is still too high to handle high frequency, high power, chip requirements.
The ideal location for decoupling capacitance is between the chip and the power supply system, on its carrier. An interposer decap or an integrated capacitor structure are both ways of achieving this ideal location. The main problem with this type of capacitor structure is that signal traces must also pass through high permittivity layers. This can contribute to unacceptably high signal to signal coupling or signal capacitance.
In an ideal capacitor structure, signals should move through low permittivity regions, while voltage and ground transmissions can move through areas of high permittivity. Such a structure enables decoupling capacitance to be delivered at the required site without the excess load of high parasitic capacitance and signal to signal coupling which might arise if signal transmission were to occur through regions of high electrical permittivity.
As semiconductor logic chips improved in performance by decreasing the cycle time and hence increasing the execution rate, it became desirable to incorporate decoupling capacitors into the circuit to reduce the effect of the noise generated at these increased switching rates and to otherwise improve overall performance. Initially these decoupling capacitors were constructed using discrete components and were mounted on a convenient location of the ceramic substrate or printed circuit board to which the chips were attached. However, as chip performance continued to improve, it became advantageous to provide low inductance paths between the capacitors and the chips.
Arnold et al. describe a low inductance electrode design for discrete capacitors in U.S. Pat. No. 4,831,494. These discrete capacitors would preferably be mounted as close to the chips as possible, on areas of the substrate adjacent to the chips for example, to further limit inductance and otherwise improve performance.
In U.S. Pat. No. 4,800,459, Takagi et al. suggest placement of discrete capacitors in substrate cavities under the chip site.
Bajorek et al. (U.S. Pat. Nos. 4,328,530 & 4,349,862) also suggested placing the decoupling capacitors in the ceramic substrate under the chip sites, but their design integrates the capacitor structures into the construction of the substrate. That is, specific regions of the ceramic multilayer structure are constructed using high dielectric constant materials and electrodes are placed on opposing sides of the high dielectric constant material to form capacitors. Bajorek, et al. also suggested that these integrated capacitors utilize specially designed low inductance electrode geometries.
Placement under the chip is the preferred location for the decoupling capacitors as it provides the shortest electrical path. Under-the-chip integrated capacitors have been described for ceramic substrate applications where the chips are wire bond connected to electrical connection pads on the substrate (U.S. Pat. Nos. 5,099,388, 5,521,332 & 5,371,403). The chips can be attached to the flat upper surface or within cavities. For substrates where chip attach is by C4 or flip-chip solder attach and the signal and power I/O (pins, ball or column grid, land grid, etc.) are on the other side; under-the-chip integrated capacitors can also be constructed.
Bajorek, et al. (U.S. Pat. Nos. 4,328,530 & 4,349,862) demonstrated capacitor placement in the ceramic multilayer substrate (which could also have thin-film wiring on the chip side surface), as did Hiroichi, et al. (U.S. Pat. No. 5,177,670).
Alternately the under-the-chip integrated capacitors can be constructed within thin-film layers on the chip side surface of the MLC substrate as described by Chance, et al. in U.S. Pat. No. 5,177,594 and Hiroichi, et al. in U.S. Pat. No. 5,177,670.
With today's extremely fast chips it is not only important to place the integrated capacitors very close to the chips with low inductance connecting paths, but to also insure that the signal wiring passes through low dielectric constant materials. With many wire bond designs, the chip and substrate I/O are on the same side of the ceramic substrate and high dielectric constant integrated capacitor layers can be placed under the chip without contacting the signal lines, as in U.S. Pat. Nos. 5,099,388 & 5,521,332. But even some wire-bond substrate designs are preferably constructed with low dielectric layers next to the chip to minimize degrading signal line performance (U.S. Pat. No. 5,371,403). However, with multilayer ceramic substrates (with or without thin-film layers) where chip connection is by C4 or flip-chip type connections, it is usually not possible to construct the substrates with layers completely consisting of high dielectric constant material(s) without having the signal lines undesirably passing through the high dielectric material. It is therefore preferable to construct capacitor containing layers using both high and low dielectric constant materials such as described in U.S. Pat. No. 5,177,670.
FIG. 1 shows the general arrangement of an interposer capacitor 10. In this figure the chip 14 is attached to the interposer 16 by standard flip chip techniques which are well known in the industry, i.e. C4 bonding as illustrated by circles 15. The interposer 16 is in turn connected using connections 17 to the carrier 18 using similar technology. Both signal and voltage connections are made from chip 14 to interposer 16 and from interposer 16 to carrier 18. Items identified as 19 are module IO, and connectors such as pins, solder, balls, etc.
FIG. 2a shows a conventional interposer capacitor 20. FIG. 2a shows a multilayer structure (a possible embodiment could be using ceramic layers) having dielectric layers 21, 22, 23. In one embodiment layers 21, 22, 23 are made of a high k material to enhance the value of the capacitance between metal electrodes 27 and 28. Passing through this structure are signal vias 25. Also passing through the dielectric layers are voltage vias 24 and 26 which are also connected to the electrodes 27 and 28 respectively. In a conventional structure the signal vias 25 would thus be in intimate contact with the high k material layers 22. To facilitate its use as an interposer, the structure 20 has pads 29 on its top surface to provide connection to a chip which could use, for example, conventional flip-chip or C4 bonding. There are also pads 30 on the bottom surface to facilitate connection to the chip carrier, either a single chip or multi-chip carrier.
FIG. 2b shows a conventional carrier-integrated capacitor 40. FIG. 2b shows a multilayer structure (a possible embodiment could be using ceramic layers) having dielectric layers 41, 42, 43, 44. In one embodiment layers 42 are made of high k material to enhance the value of the capacitance between metal electrodes 47 and 48, while layers 41, 43 and 44 could be of low k material. Passing through this structure are signal vias 45. In a conventional structure the signal vias 45 would thus be in intimate contact with the high K material of layers 42. This would add significant capacitance and coupling parasitics to the device. Also passing through the dielectric layers are voltage vias 51 and 46 which are also connected to the top most electrodes 47 and 48 respectively. Voltage vias 51 and 46 may also be connected to other metal layers (47 and 48 respectively) in the carrier. The carrier would have, as is currently practiced, pads 49 on its top surface to provide connection to a chip which could use for example flip-chip or C4 technology. There are also pads 50 on the bottom surface to facilitate connection to the next level carrier, i.e. a card or a board. Again, the carrier could be a single chip carrier or a multi-chip carrier.